Continuously reducing the size of solid-state memory architecture is an effective way to increase the capacity of such memories for a given amount of circuit real estate. However, the resulting feature size can give rise to design and process challenges. For example, the programming voltage for individual memory cells in a multi-level cell (MLC) memory architecture is relatively high in order to increase the threshold voltage Vt margin between adjacent levels. However, body bias voltage and physical size differences between pass devices in charge pump regulators coupled to global wordlines and pass devices in local wordline string drivers limit the ability to pass most of the programming voltage to the cells. This limitation tends to extract increased performance from the charge pump, perhaps beyond its design limits.
Several solutions have been attempted. However, simply matching existing device sizes in the regulator and string driver does not rectify the mismatch in a satisfactory manner, due to back-bias differences. The problem may even be enhanced because of the drain-induced-barrier lowering (DIBL) effect. In the end, the regulator device may see higher bias voltages than the string driver device, raising reliability issues.
Another solution is to add a relatively low threshold voltage diode to the regulator. However, this approach also adds voltage overhead, and even if the charge pump size is increased to provide the additional voltage, the mismatch between the global wordline voltage and the local wordline voltage may then exceed the program step voltage, resulting in additional programming pulses. Thus, there is a need for apparatus, systems, and methods that operate to more effectively pass the global wordline programming voltage to local wordlines, without increasing the size of the regulator pump or the pump output voltage magnitude.